[OpenOCD-devel] [PATCH]: 5e84f73 tcl: add hi3798CV200 target and Tocoding Poplar board config

[gerrit]

This is an automated email from Gerrit.

Peter Griffin (***@linaro.org) just uploaded a new patch set to Gerrit, which you can find at http://openocd.zylin.com/4161

-- gerrit

commit 5e84f73f201f9d98cc660e47c51cdf3dae4c6644
Author: Peter Griffin <***@linaro.org>
Date: Mon Jun 12 16:28:03 2017 +0100

tcl: add hi3798CV200 target and Tocoding Poplar board config

This config covers the 4x Cortex A53 CPUs. A custom connector
is required from J14 to standard ARM JTAG on v1 boards. However
v2 hardware should have a standard FTSH-105-01-L-DV connector.

Pinmuxing code to enable JTAG pins is included in l-loader-poplar
repository, so board is flashed with open source code, JTAG
is available at very early boot. Alternatively the following
pokes can be issued from U-Boot to enable JTAG (e.g. to debug
hisilicon SDK).

mw 0xf8a210ec 0x130;
mw 0xf8a210f0 0x130;
mw 0xf8a210f4 0x130;
mw 0xf8a210f8 0x130;
mw 0xf8a210fc 0x130;
mw 0xf8a21100 0x130;

Change-Id: I2b83dfcb3dc5461c1620f94dd99aa7b31fdda59b
Signed-off-by: Peter Griffin <***@linaro.org>

diff --git a/tcl/board/tocoding_poplar.cfg b/tcl/board/tocoding_poplar.cfg
new file mode 100644
index 0000000..4ad3bf5
--- /dev/null
+++ b/tcl/board/tocoding_poplar.cfg
@@ -0,0 +1,28 @@
+#
+# board configuration for Tocoding Poplar
+#
+
+# board does not feature anything but JTAG
+transport select jtag
+
+adapter_khz 10000
+
+# SRST-only reset configuration
+reset_config srst_only srst_push_pull
+
+source [find tcl/target/hi3798CV200.cfg]
+
+# halt the cores when gdb attaches
+${_TARGETNAME}0 configure -event gdb-attach "halt"
+
+# make sure the default target is the boot core
+targets ${_TARGETNAME}0
+
+proc core_up { args } {
+ global _TARGETNAME
+
+ # examine remaining cores
+ foreach _core [set args] {
+ ${_TARGETNAME}$_core arp_examine
+ }
+}
diff --git a/tcl/target/hi3798CV200.cfg b/tcl/target/hi3798CV200.cfg
new file mode 100644
index 0000000..5c8fbb7
--- /dev/null
+++ b/tcl/target/hi3798CV200.cfg
@@ -0,0 +1,49 @@
+# Hisilicon Hi3798CV200 Target
+
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME hi3798CV200
+}
+
+#
+# Main DAP
+#
+if { [info exists DAP_TAPID] } {
+ set _DAP_TAPID $DAP_TAPID
+} else {
+ set _DAP_TAPID 0x5ba00477
+}
+
+# declare the one JTAG tap to access the DAP
+jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -ignore-version -enable
+
+# declare the 4 main application cores
+set _TARGETNAME $_CHIPNAME.cpu
+set _smp_command ""
+
+set $_TARGETNAME.cti(0) 0x80020000
+set $_TARGETNAME.cti(1) 0x80120000
+set $_TARGETNAME.cti(2) 0x80220000
+set $_TARGETNAME.cti(3) 0x80320000
+
+set _cores 4
+for { set _core 0 } { $_core < $_cores } { incr _core 1 } {
+
+ set _command "target create ${_TARGETNAME}$_core aarch64 \
+ -chain-position $_CHIPNAME.dap -coreid $_core -ctibase [set $_TARGETNAME.cti($_core)]"
+
+ if { $_core != 0 } {
+ # non-boot core examination may fail
+ #set _command "$_command -defer-examine"
+ set _smp_command "$_smp_command ${_TARGETNAME}$_core"
+ } else {
+ # uncomment when "hawt" rtos is merged
+ # set _command "$_command -rtos hawt"
+ set _smp_command "target smp ${_TARGETNAME}$_core"
+ }
+
+ eval $_command
+}
+
+eval $_smp_command

--