[OpenOCD-devel] [openocd:tickets] #148 STM32L0x: flash size and dual bank support

[Aurelio Lucchesi]

---

** [tickets:#148] STM32L0x: flash size and dual bank support**

**Status:** new
**Milestone:** 0.9.0
**Created:** Sun Mar 19, 2017 01:47 AM UTC by Aurelio Lucchesi
**Last Updated:** Sun Mar 19, 2017 01:47 AM UTC
**Owner:** nobody


Flash programming large binaries to my STM32L082 board failed,
and I had to recompile OpenOCD in order to make it work.



Without modification, it looks like this:
~~~
$ openocd -f interface/stlink-v2.cfg -f target/stm32l0.cfg -c "program build/prj.elf reset exit verify"
...
Info : Device: STM32L0xx (Cat.5)
Info : STM32L flash has dual banks. Bank (0) size is 128kb, base address is 0x8000000
...
Error: checksum mismatch - attempting binary compare
diff 0 address 0x08020000. Was 0x3e instead of 0x69
diff 1 address 0x08020001. Was 0x79 instead of 0x21
diff 2 address 0x08020002. Was 0x79 instead of 0x3d
diff 3 address 0x08020003. Was 0x74 instead of 0x59
diff 4 address 0x08020004. Was 0x6f instead of 0x59
diff 5 address 0x08020005. Was 0x73 instead of 0x5f
...
~~~


Then I've realized that there are two flash program memory banks:

STM32L0xx category 5 MCUs come with 192 KiB of Flash program memory:
* Bank 1: starting at 0x0800 0000, size 96 KiB
* Bank 2: starting at 0x0801 8000, size 96 KiB

So I've added a second one to a copy of the stm32l0.cfg script:
~~~
# flash size will be probed
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME stm32lx 0x08000000 0 0 0 $_TARGETNAME

# add second flash bank
set _FLASHNAME $_CHIPNAME.flash1
flash bank $_FLASHNAME stm32lx 0x08018000 0x18000 0 0 $_TARGETNAME
~~~


But that revealed another problem:
~~~
$ openocd -f interface/stlink-v2.cfg -f ./stm32l0.cfg -c "program build/prj.elf reset exit verify"
...
Info : Device: STM32L0xx (Cat.5)
Info : STM32L flash has dual banks. Bank (0) size is 128kb, base address is 0x8000000
Warn : couldn't use loader, falling back to page memory writes
Info : Device: STM32L0xx (Cat.5)
Warn : STM32L flash bank base address config is incorrect. 0x8018000 but should rather be 0x8000000 or 0x8020000
Error: auto_probe failed
** Programming Failed **
shutdown command invoked
~~~


So I tried to fix things by rebuilding OpenOCD, and changed the size of
the first (and second) flash page in src/flash/nor/stm32lx.c:261 from
128 to 96 KiB:
~~~
{
.id = 0x447,
.revs = stm32_447_revs,
.num_revs = ARRAY_SIZE(stm32_447_revs),
.device_str = "STM32L0xx (Cat.5)",
.page_size = 128,
.pages_per_sector = 32,
.max_flash_size_kb = 192,
.first_bank_size_kb = 96, // 128,
.has_dual_banks = true,
.flash_base = 0x40022000,
.fsize_base = 0x1FF8007C,
},
~~~


That actually works for my hardware with the modified cfg script:
~~~
$ ~/git/openocd/src/openocd -f interface/stlink-v2.cfg -f ./stm32l0.cfg -c "program build/prj.elf reset exit verify" --search
~/git/openocd/tcl
Open On-Chip Debugger 0.10.0+dev-00093-g6b2acc02 (2017-03-18-23:04)
...
Info : Device: STM32L0xx (Cat.5)
Info : STM32L flash has dual banks. Bank (0) size is 96kb, base address is 0x8000000
Warn : couldn't use loader, falling back to page memory writes
Info : Device: STM32L0xx (Cat.5)
Info : STM32L flash has dual banks. Bank (1) size is 96kb, base address is 0x8018000
Info : ignoring flash probed value, using configured bank size: 96kbytes
...
** Verified OK **
** Resetting Target **
~~~


So I've asked on IRC and tried to submit a really simple patch for that:
http://openocd.zylin.com/#/c/4073/

But like Cezary pointed out: This **does not solve the problem of all STM32L0**
Category 5 (or 3) devices, since they all have a different memory layout...

See also:
http://openocd.zylin.com/#/c/3554/

STM32L0x1 Ref Manual: http://st.com/resource/en/reference_manual/DM00108282.pdf
STM32L0x2 Ref Manual: http://st.com/resource/en/reference_manual/DM00108281.pdf
STM32L0x3 Ref Manual: http://st.com/resource/en/reference_manual/DM00095744.pdf


I don't have access to other hardware to test things out nor enough knowledge
about OpenOCD to really fix the issue for all cases...


-----


Possible solutions that came to mind:

1) Don't use hardcoded size values. - Like Karl Palsson pointed out:
Using the probed flash size (fsize_base/flash_size_in_kb, 0x1FF8004C on STM32L0x2,
33.1.1 Flash size register) and the device ID (32.4.1 MCU device ID code,
stm32lx_read_id_code()), it should be possible to figure out the exact flash
memory layout (size, addresses, dual bank).

2) Hardcode the values for all possible combinations for all STM32L0 MCU
types/categories code the sizes.

3) Maybe the easiest: Make it possible to change first_bank_size_kb in a
config script? Or is this already possible somehow?


I'd like to help fixing this issue...


---

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[Andreas Bolsch]

The same feature (or even better - single/dual bank selectable by option bytes ...) appears e. g. in the f7 family. So you might compare this with stm32f2x.c (indeed **f2x**). There more or less variant 1) is used.


---

** [tickets:#148] STM32L0x: flash size and dual bank support**

**Status:** new
**Milestone:** 0.9.0
**Created:** Sun Mar 19, 2017 01:47 AM UTC by Aurelio Lucchesi
**Last Updated:** Sun Mar 19, 2017 01:47 AM UTC
**Owner:** nobody


Flash programming large binaries to my STM32L082 board failed,
and I had to recompile OpenOCD in order to make it work.



Without modification, it looks like this:
~~~
$ openocd -f interface/stlink-v2.cfg -f target/stm32l0.cfg -c "program build/prj.elf reset exit verify"
...
Info : Device: STM32L0xx (Cat.5)
Info : STM32L flash has dual banks. Bank (0) size is 128kb, base address is 0x8000000
...
Error: checksum mismatch - attempting binary compare
diff 0 address 0x08020000. Was 0x3e instead of 0x69
diff 1 address 0x08020001. Was 0x79 instead of 0x21
diff 2 address 0x08020002. Was 0x79 instead of 0x3d
diff 3 address 0x08020003. Was 0x74 instead of 0x59
diff 4 address 0x08020004. Was 0x6f instead of 0x59
diff 5 address 0x08020005. Was 0x73 instead of 0x5f
...
~~~


Then I've realized that there are two flash program memory banks:

STM32L0xx category 5 MCUs come with 192 KiB of Flash program memory:
* Bank 1: starting at 0x0800 0000, size 96 KiB
* Bank 2: starting at 0x0801 8000, size 96 KiB

So I've added a second one to a copy of the stm32l0.cfg script:
~~~
# flash size will be probed
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME stm32lx 0x08000000 0 0 0 $_TARGETNAME

# add second flash bank
set _FLASHNAME $_CHIPNAME.flash1
flash bank $_FLASHNAME stm32lx 0x08018000 0x18000 0 0 $_TARGETNAME
~~~


But that revealed another problem:
~~~
$ openocd -f interface/stlink-v2.cfg -f ./stm32l0.cfg -c "program build/prj.elf reset exit verify"
...
Info : Device: STM32L0xx (Cat.5)
Info : STM32L flash has dual banks. Bank (0) size is 128kb, base address is 0x8000000
Warn : couldn't use loader, falling back to page memory writes
Info : Device: STM32L0xx (Cat.5)
Warn : STM32L flash bank base address config is incorrect. 0x8018000 but should rather be 0x8000000 or 0x8020000
Error: auto_probe failed
** Programming Failed **
shutdown command invoked
~~~


So I tried to fix things by rebuilding OpenOCD, and changed the size of
the first (and second) flash page in src/flash/nor/stm32lx.c:261 from
128 to 96 KiB:
~~~
{
.id = 0x447,
.revs = stm32_447_revs,
.num_revs = ARRAY_SIZE(stm32_447_revs),
.device_str = "STM32L0xx (Cat.5)",
.page_size = 128,
.pages_per_sector = 32,
.max_flash_size_kb = 192,
.first_bank_size_kb = 96, // 128,
.has_dual_banks = true,
.flash_base = 0x40022000,
.fsize_base = 0x1FF8007C,
},
~~~


That actually works for my hardware with the modified cfg script:
~~~
$ ~/git/openocd/src/openocd -f interface/stlink-v2.cfg -f ./stm32l0.cfg -c "program build/prj.elf reset exit verify" --search
~/git/openocd/tcl
Open On-Chip Debugger 0.10.0+dev-00093-g6b2acc02 (2017-03-18-23:04)
...
Info : Device: STM32L0xx (Cat.5)
Info : STM32L flash has dual banks. Bank (0) size is 96kb, base address is 0x8000000
Warn : couldn't use loader, falling back to page memory writes
Info : Device: STM32L0xx (Cat.5)
Info : STM32L flash has dual banks. Bank (1) size is 96kb, base address is 0x8018000
Info : ignoring flash probed value, using configured bank size: 96kbytes
...
** Verified OK **
** Resetting Target **
~~~


So I've asked on IRC and tried to submit a really simple patch for that:
http://openocd.zylin.com/#/c/4073/

But like Cezary pointed out: This **does not solve the problem of all STM32L0**
Category 5 (or 3) devices, since they all have a different memory layout...

See also:
http://openocd.zylin.com/#/c/3554/

STM32L0x1 Ref Manual: http://st.com/resource/en/reference_manual/DM00108282.pdf
STM32L0x2 Ref Manual: http://st.com/resource/en/reference_manual/DM00108281.pdf
STM32L0x3 Ref Manual: http://st.com/resource/en/reference_manual/DM00095744.pdf


I don't have access to other hardware to test things out nor enough knowledge
about OpenOCD to really fix the issue for all cases...


-----


Possible solutions that came to mind:

1) Don't use hardcoded size values. - Like Karl Palsson pointed out:
Using the probed flash size (fsize_base/flash_size_in_kb, 0x1FF8004C on STM32L0x2,
33.1.1 Flash size register) and the device ID (32.4.1 MCU device ID code,
stm32lx_read_id_code()), it should be possible to figure out the exact flash
memory layout (size, addresses, dual bank).

2) Hardcode the values for all possible combinations for all STM32L0 MCU
types/categories code the sizes.

3) Maybe the easiest: Make it possible to change first_bank_size_kb in a
config script? Or is this already possible somehow?


I'd like to help fixing this issue...


---

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[Aurelio Lucchesi]

Thank you, the stm32f2x.c source file looks really comprehensive, a more detailed stm32lx_probe() function would for the STM32LX...

I don't know much about **option bytes** yet.
What are doing exactly with the (user) option bytes there?


---
Looking into those functions in stm32f2x.c:
stm32x_unlock_option_reg()
stm32x_read_options()
stm32x_write_options()

Also:
stm32x_probe()
stm32x_auto_probe()
get_stm32x_info()
...


---
And trying to figure out some things with the STM32L0x2 reference manual
(RM0376, http://st.com/resource/en/reference_manual/DM00108281.pdf)


3 Flash program memory and data EEPROM (FLASH)

3.3.1 NVM organization, Table 5. NVM organization:
0x1FF80000 - 0x1FF8001F 32 bytes User Option bytes



3.7.6 Option bytes unlock key register (FLASH_OPTKEYR)
Address offset: 0x14
-> Address: 0x40022014

3.7.8 Option bytes register (FLASH_OPTR)
Address offset 0x1C
-> Address: 0x4002201C

During production, it is set to 0x8070 00AA.

check in OpenOCD: stm32l0.cpu mdw 0x4002201C

0x4002201c 807000aa



3.7.11 Flash register map
...


3.8 Option bytes

On the NVM, an area is reserved to store a set of Option bytes which are used
to configure the product. Some option bytes are written in factory while others
can be configured by the end user.

The configuration managed by an end user is stored the Option bytes area
(32 bytes).
(...)
The Option bytes are automatically loaded during the boot. They are used to set
the content of the FLASH_OPTR and FLASH_WRPROTx registers.



The Option bytes can be read from the memory locations listed:
~~~
0x1FF80000 FLASH_OPTR[15:0]
0x1FF80004 FLASH_OPTR[31:16]
0x1FF80008 FLASH_WRPROT1[15:0]
0x1FF8000C FLASH_WRPROT1[31:16]
0x1FF80010 FLASH_WRPROT2[15:0]
~~~

Hmm...



---
Verifying some addresses and offsets in stm32l072xx.h:

~~~
/*!< Peripheral base address in the alias region */
#define PERIPH_BASE ((uint32_t)0x40000000U)
#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000U)

/*!< FLASH registers base address */
#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000U)
#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
~~~

-> Flash register base address: 0x40022000

~~~
/*!< FLASH Option Bytes base address */
#define OB_BASE ((uint32_t)0x1FF80000U)
/*!< FLASH Size register base address */
#define FLASHSIZE_BASE ((uint32_t)0x1FF8007CU)
/*!< Unique device ID register base address */
#define UID_BASE ((uint32_t)0x1FF80050U)
~~~



*just some notes*



---

** [tickets:#148] STM32L0x: flash size and dual bank support**

**Status:** new
**Milestone:** 0.9.0
**Created:** Sun Mar 19, 2017 01:47 AM UTC by Aurelio Lucchesi
**Last Updated:** Sun Mar 19, 2017 09:20 AM UTC
**Owner:** nobody


Flash programming large binaries to my STM32L082 board failed,
and I had to recompile OpenOCD in order to make it work.



Without modification, it looks like this:
~~~
$ openocd -f interface/stlink-v2.cfg -f target/stm32l0.cfg -c "program build/prj.elf reset exit verify"
...
Info : Device: STM32L0xx (Cat.5)
Info : STM32L flash has dual banks. Bank (0) size is 128kb, base address is 0x8000000
...
Error: checksum mismatch - attempting binary compare
diff 0 address 0x08020000. Was 0x3e instead of 0x69
diff 1 address 0x08020001. Was 0x79 instead of 0x21
diff 2 address 0x08020002. Was 0x79 instead of 0x3d
diff 3 address 0x08020003. Was 0x74 instead of 0x59
diff 4 address 0x08020004. Was 0x6f instead of 0x59
diff 5 address 0x08020005. Was 0x73 instead of 0x5f
...
~~~


Then I've realized that there are two flash program memory banks:

STM32L0xx category 5 MCUs come with 192 KiB of Flash program memory:
* Bank 1: starting at 0x0800 0000, size 96 KiB
* Bank 2: starting at 0x0801 8000, size 96 KiB

So I've added a second one to a copy of the stm32l0.cfg script:
~~~
# flash size will be probed
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME stm32lx 0x08000000 0 0 0 $_TARGETNAME

# add second flash bank
set _FLASHNAME $_CHIPNAME.flash1
flash bank $_FLASHNAME stm32lx 0x08018000 0x18000 0 0 $_TARGETNAME
~~~


But that revealed another problem:
~~~
$ openocd -f interface/stlink-v2.cfg -f ./stm32l0.cfg -c "program build/prj.elf reset exit verify"
...
Info : Device: STM32L0xx (Cat.5)
Info : STM32L flash has dual banks. Bank (0) size is 128kb, base address is 0x8000000
Warn : couldn't use loader, falling back to page memory writes
Info : Device: STM32L0xx (Cat.5)
Warn : STM32L flash bank base address config is incorrect. 0x8018000 but should rather be 0x8000000 or 0x8020000
Error: auto_probe failed
** Programming Failed **
shutdown command invoked
~~~


So I tried to fix things by rebuilding OpenOCD, and changed the size of
the first (and second) flash page in src/flash/nor/stm32lx.c:261 from
128 to 96 KiB:
~~~
{
.id = 0x447,
.revs = stm32_447_revs,
.num_revs = ARRAY_SIZE(stm32_447_revs),
.device_str = "STM32L0xx (Cat.5)",
.page_size = 128,
.pages_per_sector = 32,
.max_flash_size_kb = 192,
.first_bank_size_kb = 96, // 128,
.has_dual_banks = true,
.flash_base = 0x40022000,
.fsize_base = 0x1FF8007C,
},
~~~


That actually works for my hardware with the modified cfg script:
~~~
$ ~/git/openocd/src/openocd -f interface/stlink-v2.cfg -f ./stm32l0.cfg -c "program build/prj.elf reset exit verify" --search
~/git/openocd/tcl
Open On-Chip Debugger 0.10.0+dev-00093-g6b2acc02 (2017-03-18-23:04)
...
Info : Device: STM32L0xx (Cat.5)
Info : STM32L flash has dual banks. Bank (0) size is 96kb, base address is 0x8000000
Warn : couldn't use loader, falling back to page memory writes
Info : Device: STM32L0xx (Cat.5)
Info : STM32L flash has dual banks. Bank (1) size is 96kb, base address is 0x8018000
Info : ignoring flash probed value, using configured bank size: 96kbytes
...
** Verified OK **
** Resetting Target **
~~~


So I've asked on IRC and tried to submit a really simple patch for that:
http://openocd.zylin.com/#/c/4073/

But like Cezary pointed out: This **does not solve the problem of all STM32L0**
Category 5 (or 3) devices, since they all have a different memory layout...

See also:
http://openocd.zylin.com/#/c/3554/

STM32L0x1 Ref Manual: http://st.com/resource/en/reference_manual/DM00108282.pdf
STM32L0x2 Ref Manual: http://st.com/resource/en/reference_manual/DM00108281.pdf
STM32L0x3 Ref Manual: http://st.com/resource/en/reference_manual/DM00095744.pdf


I don't have access to other hardware to test things out nor enough knowledge
about OpenOCD to really fix the issue for all cases...


-----


Possible solutions that came to mind:

1) Don't use hardcoded size values. - Like Karl Palsson pointed out:
Using the probed flash size (fsize_base/flash_size_in_kb, 0x1FF8004C on STM32L0x2,
33.1.1 Flash size register) and the device ID (32.4.1 MCU device ID code,
stm32lx_read_id_code()), it should be possible to figure out the exact flash
memory layout (size, addresses, dual bank).

2) Hardcode the values for all possible combinations for all STM32L0 MCU
types/categories code the sizes.

3) Maybe the easiest: Make it possible to change first_bank_size_kb in a
config script? Or is this already possible somehow?


I'd like to help fixing this issue...


---

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[Aurelio Lucchesi]

Ah, bit OPTCR_DB1M of the STM32_FLASH_OPTCR is used on stm32f2x.c:930 to determine of the MCU has one or two flash banks... (42x/43x/469/479 1024 kiByte devices).

And bit OPTCR_NDBANK of STM32_FLASH_OPTCR for F76x/77x devices right below.

~~~
/* Devices with > 1024 kiByte always are dual-banked */
if (flash_size_in_kb > 1024)
stm32x_info->has_large_mem = true;

/* F42x/43x/469/479 1024 kiByte devices have a dual bank option */
if ((device_id & 0xfff) == 0x419 || (device_id & 0xfff) == 0x434) {
uint32_t optiondata;
retval = target_read_u32(target, STM32_FLASH_OPTCR, &optiondata);
if (retval != ERROR_OK) {
LOG_DEBUG("unable to read option bytes");
return retval;
}
if ((flash_size_in_kb > 1024) || (optiondata & OPTCR_DB1M)) {
stm32x_info->has_large_mem = true;
LOG_INFO("Dual Bank %d kiB STM32F42x/43x/469/479 found", flash_size_in_kb);
} else {
stm32x_info->has_large_mem = false;
LOG_INFO("Single Bank %d kiB STM32F42x/43x/469/479 found", flash_size_in_kb);
}
}

/* F76x/77x devices have a dual bank option */
if ((device_id & 0xfff) == 0x451) {
uint32_t optiondata;
retval = target_read_u32(target, STM32_FLASH_OPTCR, &optiondata);
if (retval != ERROR_OK) {
LOG_DEBUG("unable to read option bytes");
return retval;
}
if (optiondata & OPTCR_NDBANK) {
stm32x_info->has_large_mem = false;
LOG_INFO("Single Bank %d kiB STM32F76x/77x found", flash_size_in_kb);
} else {
stm32x_info->has_large_mem = true;
max_sector_size_in_kb >>= 1; /* sector size divided by 2 in dual-bank mode */
LOG_INFO("Dual Bank %d kiB STM32F76x/77x found", flash_size_in_kb);
}
}
~~~

*Trying to figure out if that is possible for STM32Lx MCUs as well...*


---

** [tickets:#148] STM32L0x: flash size and dual bank support**

**Status:** new
**Milestone:** 0.9.0
**Created:** Sun Mar 19, 2017 01:47 AM UTC by Aurelio Lucchesi
**Last Updated:** Sun Mar 19, 2017 03:42 PM UTC
**Owner:** nobody


Flash programming large binaries to my STM32L082 board failed,
and I had to recompile OpenOCD in order to make it work.



Without modification, it looks like this:
~~~
$ openocd -f interface/stlink-v2.cfg -f target/stm32l0.cfg -c "program build/prj.elf reset exit verify"
...
Info : Device: STM32L0xx (Cat.5)
Info : STM32L flash has dual banks. Bank (0) size is 128kb, base address is 0x8000000
...
Error: checksum mismatch - attempting binary compare
diff 0 address 0x08020000. Was 0x3e instead of 0x69
diff 1 address 0x08020001. Was 0x79 instead of 0x21
diff 2 address 0x08020002. Was 0x79 instead of 0x3d
diff 3 address 0x08020003. Was 0x74 instead of 0x59
diff 4 address 0x08020004. Was 0x6f instead of 0x59
diff 5 address 0x08020005. Was 0x73 instead of 0x5f
...
~~~


Then I've realized that there are two flash program memory banks:

STM32L0xx category 5 MCUs come with 192 KiB of Flash program memory:
* Bank 1: starting at 0x0800 0000, size 96 KiB
* Bank 2: starting at 0x0801 8000, size 96 KiB

So I've added a second one to a copy of the stm32l0.cfg script:
~~~
# flash size will be probed
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME stm32lx 0x08000000 0 0 0 $_TARGETNAME

# add second flash bank
set _FLASHNAME $_CHIPNAME.flash1
flash bank $_FLASHNAME stm32lx 0x08018000 0x18000 0 0 $_TARGETNAME
~~~


But that revealed another problem:
~~~
$ openocd -f interface/stlink-v2.cfg -f ./stm32l0.cfg -c "program build/prj.elf reset exit verify"
...
Info : Device: STM32L0xx (Cat.5)
Info : STM32L flash has dual banks. Bank (0) size is 128kb, base address is 0x8000000
Warn : couldn't use loader, falling back to page memory writes
Info : Device: STM32L0xx (Cat.5)
Warn : STM32L flash bank base address config is incorrect. 0x8018000 but should rather be 0x8000000 or 0x8020000
Error: auto_probe failed
** Programming Failed **
shutdown command invoked
~~~


So I tried to fix things by rebuilding OpenOCD, and changed the size of
the first (and second) flash page in src/flash/nor/stm32lx.c:261 from
128 to 96 KiB:
~~~
{
.id = 0x447,
.revs = stm32_447_revs,
.num_revs = ARRAY_SIZE(stm32_447_revs),
.device_str = "STM32L0xx (Cat.5)",
.page_size = 128,
.pages_per_sector = 32,
.max_flash_size_kb = 192,
.first_bank_size_kb = 96, // 128,
.has_dual_banks = true,
.flash_base = 0x40022000,
.fsize_base = 0x1FF8007C,
},
~~~


That actually works for my hardware with the modified cfg script:
~~~
$ ~/git/openocd/src/openocd -f interface/stlink-v2.cfg -f ./stm32l0.cfg -c "program build/prj.elf reset exit verify" --search
~/git/openocd/tcl
Open On-Chip Debugger 0.10.0+dev-00093-g6b2acc02 (2017-03-18-23:04)
...
Info : Device: STM32L0xx (Cat.5)
Info : STM32L flash has dual banks. Bank (0) size is 96kb, base address is 0x8000000
Warn : couldn't use loader, falling back to page memory writes
Info : Device: STM32L0xx (Cat.5)
Info : STM32L flash has dual banks. Bank (1) size is 96kb, base address is 0x8018000
Info : ignoring flash probed value, using configured bank size: 96kbytes
...
** Verified OK **
** Resetting Target **
~~~


So I've asked on IRC and tried to submit a really simple patch for that:
http://openocd.zylin.com/#/c/4073/

But like Cezary pointed out: This **does not solve the problem of all STM32L0**
Category 5 (or 3) devices, since they all have a different memory layout...

See also:
http://openocd.zylin.com/#/c/3554/

STM32L0x1 Ref Manual: http://st.com/resource/en/reference_manual/DM00108282.pdf
STM32L0x2 Ref Manual: http://st.com/resource/en/reference_manual/DM00108281.pdf
STM32L0x3 Ref Manual: http://st.com/resource/en/reference_manual/DM00095744.pdf


I don't have access to other hardware to test things out nor enough knowledge
about OpenOCD to really fix the issue for all cases...


-----


Possible solutions that came to mind:

1) Don't use hardcoded size values. - Like Karl Palsson pointed out:
Using the probed flash size (fsize_base/flash_size_in_kb, 0x1FF8004C on STM32L0x2,
33.1.1 Flash size register) and the device ID (32.4.1 MCU device ID code,
stm32lx_read_id_code()), it should be possible to figure out the exact flash
memory layout (size, addresses, dual bank).

2) Hardcode the values for all possible combinations for all STM32L0 MCU
types/categories code the sizes.

3) Maybe the easiest: Make it possible to change first_bank_size_kb in a
config script? Or is this already possible somehow?


I'd like to help fixing this issue...


---

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[Cezary Gapiński]

I've selected the types of memory layouts from reference manuals:

STM32L0x1 Ref Manual: http://st.com/resource/en/reference_manual/DM00108282.pdf

Table 5. NVM organization (category 1 devices)
Single bank - 16 KBytes
Table 6. NVM organization (category 2 devices)
Single bank - 32 KBytes
Table 7. NVM organization (category 3 devices)
Single bank - 64 KBytes
**Table 8. NVM organization for UFB = 0 (192 Kbyte category 5 devices) - id = 0x447 STM32L0xx (Cat.5)
Dual bank - 96 Kbytes for bank
Table 10. NVM organization for UFB = 0 (128 Kbyte category 5 devices) - id = 0x447 STM32L0xx (Cat.5)
Dual bank - 64 Kbytes for bank**
Table 12. NVM organization for UFB = 0 (64 Kbyte category 5 devices)
Single bank - 64 KBytes

STM32L0x2 Ref Manual: http://st.com/resource/en/reference_manual/DM00108281.pdf
STM32L0x3 Ref Manual: http://st.com/resource/en/reference_manual/DM00095744.pdf

Table 5. NVM organization (category 3 devices)
Single bank - 64 KBytes
**Table 6. NVM organization for UFB = 0 (192 Kbyte category 5 devices) - id = 0x447 STM32L0xx (Cat.5)
Dual bank - 96 Kbytes for bank
Table 8. NVM organization for UFB = 0 (128 Kbyte category 5 devices) - id = 0x447 STM32L0xx (Cat.5)
Dual bank - 64 Kbytes for bank**
Table 10. NVM organization for UFB = 0 (64 Kbyte category 5 devices)
Single bank - 64 KBytes

STM32Lxxxx Ref Manual: http://st.com/resource/en/reference_manual/CD00240193.pdf

Table 8. NVM module organization (Cat.1 and Cat.2 devices)
Single bank - 128 KBytes
Table 9. NVM module organization (Cat.3 devices)
Single bank - 256 KBytes
**Table 10. NVM module organization (Cat.4 devices) - id = 0x436 STM32L1xx (Cat.4/Cat.3 - Medium+/High Density)
Dual bank - 192 Kbytes for bank
Table 11. NVM module organization (Cat.5 devices) - id = 0x437 STM32L1xx (Cat.5/Cat.6)
Dual bank - 256 Kbytes for bank
Table 12. NVM module organization (Cat.6 devices) - id = 0x437 STM32L1xx (Cat.5/Cat.6)
Dual bank - 192 Kbytes for bank**

id = 0x447 STM32L0xx (Cat.5) <- dual bank, for flash size 192 or 128 KBytes, single bank for 64 KBytes
id = 0x436 STM32L1xx (Cat.4/Cat.3 - Medium+/High Density) <- only one size of bank, default values are correct
id = 0x437 STM32L1xx (Cat.5/Cat.6) <- always dual bank, but size of bank can be different

Perhaps is easier to base on memory sizes and ids to select correct bank size values like here: http://openocd.zylin.com/#/c/4074/
?
Or of course if you will have more clear idea with option bytes usage, I will be also perfectly happy to use your solution :).


---

** [tickets:#148] STM32L0x: flash size and dual bank support**

**Status:** new
**Milestone:** 0.9.0
**Created:** Sun Mar 19, 2017 01:47 AM UTC by Aurelio Lucchesi
**Last Updated:** Sun Mar 19, 2017 03:42 PM UTC
**Owner:** nobody


Flash programming large binaries to my STM32L082 board failed,
and I had to recompile OpenOCD in order to make it work.



Without modification, it looks like this:
~~~
$ openocd -f interface/stlink-v2.cfg -f target/stm32l0.cfg -c "program build/prj.elf reset exit verify"
...
Info : Device: STM32L0xx (Cat.5)
Info : STM32L flash has dual banks. Bank (0) size is 128kb, base address is 0x8000000
...
Error: checksum mismatch - attempting binary compare
diff 0 address 0x08020000. Was 0x3e instead of 0x69
diff 1 address 0x08020001. Was 0x79 instead of 0x21
diff 2 address 0x08020002. Was 0x79 instead of 0x3d
diff 3 address 0x08020003. Was 0x74 instead of 0x59
diff 4 address 0x08020004. Was 0x6f instead of 0x59
diff 5 address 0x08020005. Was 0x73 instead of 0x5f
...
~~~


Then I've realized that there are two flash program memory banks:

STM32L0xx category 5 MCUs come with 192 KiB of Flash program memory:
* Bank 1: starting at 0x0800 0000, size 96 KiB
* Bank 2: starting at 0x0801 8000, size 96 KiB

So I've added a second one to a copy of the stm32l0.cfg script:
~~~
# flash size will be probed
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME stm32lx 0x08000000 0 0 0 $_TARGETNAME

# add second flash bank
set _FLASHNAME $_CHIPNAME.flash1
flash bank $_FLASHNAME stm32lx 0x08018000 0x18000 0 0 $_TARGETNAME
~~~


But that revealed another problem:
~~~
$ openocd -f interface/stlink-v2.cfg -f ./stm32l0.cfg -c "program build/prj.elf reset exit verify"
...
Info : Device: STM32L0xx (Cat.5)
Info : STM32L flash has dual banks. Bank (0) size is 128kb, base address is 0x8000000
Warn : couldn't use loader, falling back to page memory writes
Info : Device: STM32L0xx (Cat.5)
Warn : STM32L flash bank base address config is incorrect. 0x8018000 but should rather be 0x8000000 or 0x8020000
Error: auto_probe failed
** Programming Failed **
shutdown command invoked
~~~


So I tried to fix things by rebuilding OpenOCD, and changed the size of
the first (and second) flash page in src/flash/nor/stm32lx.c:261 from
128 to 96 KiB:
~~~
{
.id = 0x447,
.revs = stm32_447_revs,
.num_revs = ARRAY_SIZE(stm32_447_revs),
.device_str = "STM32L0xx (Cat.5)",
.page_size = 128,
.pages_per_sector = 32,
.max_flash_size_kb = 192,
.first_bank_size_kb = 96, // 128,
.has_dual_banks = true,
.flash_base = 0x40022000,
.fsize_base = 0x1FF8007C,
},
~~~


That actually works for my hardware with the modified cfg script:
~~~
$ ~/git/openocd/src/openocd -f interface/stlink-v2.cfg -f ./stm32l0.cfg -c "program build/prj.elf reset exit verify" --search
~/git/openocd/tcl
Open On-Chip Debugger 0.10.0+dev-00093-g6b2acc02 (2017-03-18-23:04)
...
Info : Device: STM32L0xx (Cat.5)
Info : STM32L flash has dual banks. Bank (0) size is 96kb, base address is 0x8000000
Warn : couldn't use loader, falling back to page memory writes
Info : Device: STM32L0xx (Cat.5)
Info : STM32L flash has dual banks. Bank (1) size is 96kb, base address is 0x8018000
Info : ignoring flash probed value, using configured bank size: 96kbytes
...
** Verified OK **
** Resetting Target **
~~~


So I've asked on IRC and tried to submit a really simple patch for that:
http://openocd.zylin.com/#/c/4073/

But like Cezary pointed out: This **does not solve the problem of all STM32L0**
Category 5 (or 3) devices, since they all have a different memory layout...

See also:
http://openocd.zylin.com/#/c/3554/

STM32L0x1 Ref Manual: http://st.com/resource/en/reference_manual/DM00108282.pdf
STM32L0x2 Ref Manual: http://st.com/resource/en/reference_manual/DM00108281.pdf
STM32L0x3 Ref Manual: http://st.com/resource/en/reference_manual/DM00095744.pdf


I don't have access to other hardware to test things out nor enough knowledge
about OpenOCD to really fix the issue for all cases...


-----


Possible solutions that came to mind:

1) Don't use hardcoded size values. - Like Karl Palsson pointed out:
Using the probed flash size (fsize_base/flash_size_in_kb, 0x1FF8004C on STM32L0x2,
33.1.1 Flash size register) and the device ID (32.4.1 MCU device ID code,
stm32lx_read_id_code()), it should be possible to figure out the exact flash
memory layout (size, addresses, dual bank).

2) Hardcode the values for all possible combinations for all STM32L0 MCU
types/categories code the sizes.

3) Maybe the easiest: Make it possible to change first_bank_size_kb in a
config script? Or is this already possible somehow?


I'd like to help fixing this issue...


---

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[Aurelio Lucchesi]

Hi Cezary, thanks for the summary of the memory layouts, this is what I panned to look into as well...

At the moment I'm trying out your patch: http://openocd.zylin.com/#/c/4074/

http://openocd.zylin.com/#/c/4074/2/src/flash/nor/stm32lx.c

It looks like a nice solution and works for my STM32L082! (Are really all variants covered?)

The only thing I needed to add was the config file, to tell OpenOCD that there is second flash bank.
~~~

~/git/openocd/src/openocd -f interface/stlink-v2.cfg -f ./stm32l0x2.cfg -c "program build/prj.elf verify reset exit" --search ~/git/openocd/tcl

$ tail -n+72 stm32l0x2.cfg | head -n5
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME stm32lx 0x08000000 0 0 0 $_TARGETNAME

set _FLASHNAME $_CHIPNAME.flash1
flash bank $_FLASHNAME stm32lx 0x08018000 0 0 0 $_TARGETNAME
~~~

Luckily the size will be determined by OpenOCD. So, do you think this would work for a all STM32L0xs on the list?

If so, we might add a very similar CFG file for the L0x, like that one: openocd/tcl/target/stm32l1x_dual_bank.cfg.

~~~
$ cat stm32l0x_dual_bank.cfg
source [find target/stm32l0.cfg]

# The stm32l0x might have a dual bank flash.
# Let's add a definition for the second bank here.

# Add the second flash bank.
set _FLASHNAME $_CHIPNAME.flash1
flash bank $_FLASHNAME stm32lx 0 0 0 0 $_TARGETNAME
~~~

*But what about the the L0s that don't have two flash banks?* Is it up to the user to decide whether to use stm32l0.cfg or stm32l0x_dual_bank.cfg ? - The latter would only be needed for large binaries, otherwise the stm32l0.cfg would work fine?


Jan Čapek also worked on a solution for the same problem: http://openocd.zylin.com/#/c/4076/2


---

** [tickets:#148] STM32L0x: flash size and dual bank support**

**Status:** new
**Milestone:** 0.9.0
**Created:** Sun Mar 19, 2017 01:47 AM UTC by Aurelio Lucchesi
**Last Updated:** Mon Mar 20, 2017 12:04 PM UTC
**Owner:** nobody


Flash programming large binaries to my STM32L082 board failed,
and I had to recompile OpenOCD in order to make it work.



Without modification, it looks like this:
~~~
$ openocd -f interface/stlink-v2.cfg -f target/stm32l0.cfg -c "program build/prj.elf reset exit verify"
...
Info : Device: STM32L0xx (Cat.5)
Info : STM32L flash has dual banks. Bank (0) size is 128kb, base address is 0x8000000
...
Error: checksum mismatch - attempting binary compare
diff 0 address 0x08020000. Was 0x3e instead of 0x69
diff 1 address 0x08020001. Was 0x79 instead of 0x21
diff 2 address 0x08020002. Was 0x79 instead of 0x3d
diff 3 address 0x08020003. Was 0x74 instead of 0x59
diff 4 address 0x08020004. Was 0x6f instead of 0x59
diff 5 address 0x08020005. Was 0x73 instead of 0x5f
...
~~~


Then I've realized that there are two flash program memory banks:

STM32L0xx category 5 MCUs come with 192 KiB of Flash program memory:
* Bank 1: starting at 0x0800 0000, size 96 KiB
* Bank 2: starting at 0x0801 8000, size 96 KiB

So I've added a second one to a copy of the stm32l0.cfg script:
~~~
# flash size will be probed
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME stm32lx 0x08000000 0 0 0 $_TARGETNAME

# add second flash bank
set _FLASHNAME $_CHIPNAME.flash1
flash bank $_FLASHNAME stm32lx 0x08018000 0x18000 0 0 $_TARGETNAME
~~~


But that revealed another problem:
~~~
$ openocd -f interface/stlink-v2.cfg -f ./stm32l0.cfg -c "program build/prj.elf reset exit verify"
...
Info : Device: STM32L0xx (Cat.5)
Info : STM32L flash has dual banks. Bank (0) size is 128kb, base address is 0x8000000
Warn : couldn't use loader, falling back to page memory writes
Info : Device: STM32L0xx (Cat.5)
Warn : STM32L flash bank base address config is incorrect. 0x8018000 but should rather be 0x8000000 or 0x8020000
Error: auto_probe failed
** Programming Failed **
shutdown command invoked
~~~


So I tried to fix things by rebuilding OpenOCD, and changed the size of
the first (and second) flash page in src/flash/nor/stm32lx.c:261 from
128 to 96 KiB:
~~~
{
.id = 0x447,
.revs = stm32_447_revs,
.num_revs = ARRAY_SIZE(stm32_447_revs),
.device_str = "STM32L0xx (Cat.5)",
.page_size = 128,
.pages_per_sector = 32,
.max_flash_size_kb = 192,
.first_bank_size_kb = 96, // 128,
.has_dual_banks = true,
.flash_base = 0x40022000,
.fsize_base = 0x1FF8007C,
},
~~~


That actually works for my hardware with the modified cfg script:
~~~
$ ~/git/openocd/src/openocd -f interface/stlink-v2.cfg -f ./stm32l0.cfg -c "program build/prj.elf reset exit verify" --search
~/git/openocd/tcl
Open On-Chip Debugger 0.10.0+dev-00093-g6b2acc02 (2017-03-18-23:04)
...
Info : Device: STM32L0xx (Cat.5)
Info : STM32L flash has dual banks. Bank (0) size is 96kb, base address is 0x8000000
Warn : couldn't use loader, falling back to page memory writes
Info : Device: STM32L0xx (Cat.5)
Info : STM32L flash has dual banks. Bank (1) size is 96kb, base address is 0x8018000
Info : ignoring flash probed value, using configured bank size: 96kbytes
...
** Verified OK **
** Resetting Target **
~~~


So I've asked on IRC and tried to submit a really simple patch for that:
http://openocd.zylin.com/#/c/4073/

But like Cezary pointed out: This **does not solve the problem of all STM32L0**
Category 5 (or 3) devices, since they all have a different memory layout...

See also:
http://openocd.zylin.com/#/c/3554/

STM32L0x1 Ref Manual: http://st.com/resource/en/reference_manual/DM00108282.pdf
STM32L0x2 Ref Manual: http://st.com/resource/en/reference_manual/DM00108281.pdf
STM32L0x3 Ref Manual: http://st.com/resource/en/reference_manual/DM00095744.pdf


I don't have access to other hardware to test things out nor enough knowledge
about OpenOCD to really fix the issue for all cases...


-----


Possible solutions that came to mind:

1) Don't use hardcoded size values. - Like Karl Palsson pointed out:
Using the probed flash size (fsize_base/flash_size_in_kb, 0x1FF8004C on STM32L0x2,
33.1.1 Flash size register) and the device ID (32.4.1 MCU device ID code,
stm32lx_read_id_code()), it should be possible to figure out the exact flash
memory layout (size, addresses, dual bank).

2) Hardcode the values for all possible combinations for all STM32L0 MCU
types/categories code the sizes.

3) Maybe the easiest: Make it possible to change first_bank_size_kb in a
config script? Or is this already possible somehow?


I'd like to help fixing this issue...


---

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[Aurelio Lucchesi]

Correction: It **does not need a special CFG file**, since the patch actually already figures that out, I see...


---

** [tickets:#148] STM32L0x: flash size and dual bank support**

**Status:** new
**Milestone:** 0.9.0
**Created:** Sun Mar 19, 2017 01:47 AM UTC by Aurelio Lucchesi
**Last Updated:** Tue Mar 21, 2017 11:10 AM UTC
**Owner:** nobody


Flash programming large binaries to my STM32L082 board failed,
and I had to recompile OpenOCD in order to make it work.



Without modification, it looks like this:
~~~
$ openocd -f interface/stlink-v2.cfg -f target/stm32l0.cfg -c "program build/prj.elf reset exit verify"
...
Info : Device: STM32L0xx (Cat.5)
Info : STM32L flash has dual banks. Bank (0) size is 128kb, base address is 0x8000000
...
Error: checksum mismatch - attempting binary compare
diff 0 address 0x08020000. Was 0x3e instead of 0x69
diff 1 address 0x08020001. Was 0x79 instead of 0x21
diff 2 address 0x08020002. Was 0x79 instead of 0x3d
diff 3 address 0x08020003. Was 0x74 instead of 0x59
diff 4 address 0x08020004. Was 0x6f instead of 0x59
diff 5 address 0x08020005. Was 0x73 instead of 0x5f
...
~~~


Then I've realized that there are two flash program memory banks:

STM32L0xx category 5 MCUs come with 192 KiB of Flash program memory:
* Bank 1: starting at 0x0800 0000, size 96 KiB
* Bank 2: starting at 0x0801 8000, size 96 KiB

So I've added a second one to a copy of the stm32l0.cfg script:
~~~
# flash size will be probed
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME stm32lx 0x08000000 0 0 0 $_TARGETNAME

# add second flash bank
set _FLASHNAME $_CHIPNAME.flash1
flash bank $_FLASHNAME stm32lx 0x08018000 0x18000 0 0 $_TARGETNAME
~~~


But that revealed another problem:
~~~
$ openocd -f interface/stlink-v2.cfg -f ./stm32l0.cfg -c "program build/prj.elf reset exit verify"
...
Info : Device: STM32L0xx (Cat.5)
Info : STM32L flash has dual banks. Bank (0) size is 128kb, base address is 0x8000000
Warn : couldn't use loader, falling back to page memory writes
Info : Device: STM32L0xx (Cat.5)
Warn : STM32L flash bank base address config is incorrect. 0x8018000 but should rather be 0x8000000 or 0x8020000
Error: auto_probe failed
** Programming Failed **
shutdown command invoked
~~~


So I tried to fix things by rebuilding OpenOCD, and changed the size of
the first (and second) flash page in src/flash/nor/stm32lx.c:261 from
128 to 96 KiB:
~~~
{
.id = 0x447,
.revs = stm32_447_revs,
.num_revs = ARRAY_SIZE(stm32_447_revs),
.device_str = "STM32L0xx (Cat.5)",
.page_size = 128,
.pages_per_sector = 32,
.max_flash_size_kb = 192,
.first_bank_size_kb = 96, // 128,
.has_dual_banks = true,
.flash_base = 0x40022000,
.fsize_base = 0x1FF8007C,
},
~~~


That actually works for my hardware with the modified cfg script:
~~~
$ ~/git/openocd/src/openocd -f interface/stlink-v2.cfg -f ./stm32l0.cfg -c "program build/prj.elf reset exit verify" --search
~/git/openocd/tcl
Open On-Chip Debugger 0.10.0+dev-00093-g6b2acc02 (2017-03-18-23:04)
...
Info : Device: STM32L0xx (Cat.5)
Info : STM32L flash has dual banks. Bank (0) size is 96kb, base address is 0x8000000
Warn : couldn't use loader, falling back to page memory writes
Info : Device: STM32L0xx (Cat.5)
Info : STM32L flash has dual banks. Bank (1) size is 96kb, base address is 0x8018000
Info : ignoring flash probed value, using configured bank size: 96kbytes
...
** Verified OK **
** Resetting Target **
~~~


So I've asked on IRC and tried to submit a really simple patch for that:
http://openocd.zylin.com/#/c/4073/

But like Cezary pointed out: This **does not solve the problem of all STM32L0**
Category 5 (or 3) devices, since they all have a different memory layout...

See also:
http://openocd.zylin.com/#/c/3554/

STM32L0x1 Ref Manual: http://st.com/resource/en/reference_manual/DM00108282.pdf
STM32L0x2 Ref Manual: http://st.com/resource/en/reference_manual/DM00108281.pdf
STM32L0x3 Ref Manual: http://st.com/resource/en/reference_manual/DM00095744.pdf


I don't have access to other hardware to test things out nor enough knowledge
about OpenOCD to really fix the issue for all cases...


-----


Possible solutions that came to mind:

1) Don't use hardcoded size values. - Like Karl Palsson pointed out:
Using the probed flash size (fsize_base/flash_size_in_kb, 0x1FF8004C on STM32L0x2,
33.1.1 Flash size register) and the device ID (32.4.1 MCU device ID code,
stm32lx_read_id_code()), it should be possible to figure out the exact flash
memory layout (size, addresses, dual bank).

2) Hardcode the values for all possible combinations for all STM32L0 MCU
types/categories code the sizes.

3) Maybe the easiest: Make it possible to change first_bank_size_kb in a
config script? Or is this already possible somehow?


I'd like to help fixing this issue...


---

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[Cezary Gapiński]

Hi Cezary, thanks for the summary of the memory layouts, this is what I planned to look into as well :)
At the moment I'm trying out your patch: http://openocd.zylin.com/#/c/4074/
http://openocd.zylin.com/#/c/4074/2/src/flash/nor/stm32lx.c
It looks like a nice solution and works for my STM32L082 board! (Are really all variants covered?)

I hope so, that it should works for all listed devices if the reference manuals from ST are correct and I didn't have make any mistake :).

But what about the the L0s that don't have two flash banks? Is it up to the user to decide whether to use stm32l0.cfg or stm32l0x_dual_bank.cfg ? - The latter would only be needed for large binaries, otherwise the stm32l0.cfg would work fine?

I think that always correct cfg file should be used for the MCU. If device has two banks that stm32l0x_dual_bank.cfg also should be used without any dependency of binaries size. Please notice that dual bank can be used also when binaries are smaller but someone need to boot up device from second bank like for example in 3.3.2 Dual-bank boot capability (RM0377).

Jan Čapek also worked on a solution for the same problem: http://openocd.zylin.com/#/c/4076/2

I know and I noticed that is not fully solve the problem (with links to yours and my patch). You can also write a post for his change and that you have tried to solve this problem earlier.

Correction: Not sure if it needs a special CFG file, since the patch actually already figures out if the MCU has a dual bank layout...
Info : Device: STM32L0xx (Cat.5)
Info : STM32L flash has dual banks. Bank (0) size is 96kb, base address is 0x8000000
But then fails writing beyond 0x08018000 (second bank)...
Warn : no flash bank found for address 8018000
Warn : no flash bank found for address 8025ff4
Here, a full print out (with usual warnings, and actual errors)..
$ ~/git/openocd/src/openocd -f interface/stlink-v2.cfg -f target/stm32l0.cfg -c "program build/prj.elf verify reset exit" --search ~/git/openocd/tcl
Open On-Chip Debugger 0.10.0+dev-00094-gfc738c70 (2017-03-21-11:32)
Licensed under GNU GPL v2
For bug reports, read
http://openocd.org/doc/doxygen/bugs.html
Info : auto-selecting first available session transport "hla_swd". To override use 'transport select <transport>'.
adapter speed: 300 kHz
adapter_nsrst_delay: 100
Info : The selected transport took over low-level target control. The results might differ compared to plain JTAG/SWD
none separate
Info : Unable to match requested speed 300 kHz, using 240 kHz
Info : Unable to match requested speed 300 kHz, using 240 kHz
Info : clock speed 240 kHz
Info : STLINK v2 JTAG v17 API v2 SWIM v4 VID 0x0483 PID 0x3748
Info : using stlink api v2
Info : Target voltage: 3.485039
Info : stm32l0.cpu: hardware has 4 breakpoints, 2 watchpoints
adapter speed: 300 kHz
target halted due to debug-request, current mode: Thread
xPSR: 0xf1000000 pc: 0x08018e14 msp: 0x20005000
STM32L0: Enabling HSI16
adapter speed: 2500 kHz
** Programming Started **
auto erase enabled
Info : Device: STM32L0xx (Cat.5)
Info : STM32L flash has dual banks. Bank (0) size is 96kb, base address is 0x8000000
Warn : couldn't use loader, falling back to page memory writes
Warn : no flash bank found for address 8018000
Warn : no flash bank found for address 8025ff4
wrote 98304 bytes from file build/prj.elf in 37.422348s (2.565 KiB/s)
** Programming Finished **
** Verify Started **
Error: JTAG failure
Error: Error setting register
target halted due to breakpoint, current mode: Handler HardFault
xPSR: 0x61000003 pc: 0x2000002e msp: 0x20005000
Error: JTAG failure
Error: Error setting register
target halted due to breakpoint, current mode: Handler HardFault
xPSR: 0x61000003 pc: 0x2000002e msp: 0x20005000
verified 156464 bytes in 0.970004s (157.522 KiB/s)
** Verified OK **
** Resetting Target **
adapter speed: 300 kHz
shutdown command invoked

Hmm, I'm not sure but for me that works correctly. Can you show the stm32l0.cfg file?

http://openocd.zylin.com/#/c/3554/3/tcl/target/stm32l0_192KB_dual_bank.cfg
# The stm32l0 192 Kbyte category 5 devices dual bank flash.
# Overwritting a definition for the first and add second bank here.
set FLASHSIZE 98304
source [find target/stm32l0.cfg]
# Add the second flash bank.
set _FLASHNAME $_CHIPNAME.flash1
flash bank $_FLASHNAME stm32lx 0 $FLASHSIZE 0 0 $_TARGETNAME
Would it necessary to specify the size? Wouldn't 0 let OpenOCD determine the size by your new patch?

For the first glance this file works for me and I don't have any warnings. Please notice that this patch (http://openocd.zylin.com/#/c/3554) is canceled because of new patch.
Jan Čapek created good config files for NUCLEO-L073RZ here:
http://openocd.zylin.com/#/c/3957/ and here the flash memory size is leaved to zero value.

BTW, you are using STM32L082 on custom board or this is some sort of evaluation board. If it's eval board perhaps you can create a patch with yout board configuration?




---

** [tickets:#148] STM32L0x: flash size and dual bank support**

**Status:** new
**Milestone:** 0.9.0
**Created:** Sun Mar 19, 2017 01:47 AM UTC by Aurelio Lucchesi
**Last Updated:** Tue Mar 21, 2017 11:18 AM UTC
**Owner:** nobody


Flash programming large binaries to my STM32L082 board failed,
and I had to recompile OpenOCD in order to make it work.



Without modification, it looks like this:
~~~
$ openocd -f interface/stlink-v2.cfg -f target/stm32l0.cfg -c "program build/prj.elf reset exit verify"
...
Info : Device: STM32L0xx (Cat.5)
Info : STM32L flash has dual banks. Bank (0) size is 128kb, base address is 0x8000000
...
Error: checksum mismatch - attempting binary compare
diff 0 address 0x08020000. Was 0x3e instead of 0x69
diff 1 address 0x08020001. Was 0x79 instead of 0x21
diff 2 address 0x08020002. Was 0x79 instead of 0x3d
diff 3 address 0x08020003. Was 0x74 instead of 0x59
diff 4 address 0x08020004. Was 0x6f instead of 0x59
diff 5 address 0x08020005. Was 0x73 instead of 0x5f
...
~~~


Then I've realized that there are two flash program memory banks:

STM32L0xx category 5 MCUs come with 192 KiB of Flash program memory:
* Bank 1: starting at 0x0800 0000, size 96 KiB
* Bank 2: starting at 0x0801 8000, size 96 KiB

So I've added a second one to a copy of the stm32l0.cfg script:
~~~
# flash size will be probed
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME stm32lx 0x08000000 0 0 0 $_TARGETNAME

# add second flash bank
set _FLASHNAME $_CHIPNAME.flash1
flash bank $_FLASHNAME stm32lx 0x08018000 0x18000 0 0 $_TARGETNAME
~~~


But that revealed another problem:
~~~
$ openocd -f interface/stlink-v2.cfg -f ./stm32l0.cfg -c "program build/prj.elf reset exit verify"
...
Info : Device: STM32L0xx (Cat.5)
Info : STM32L flash has dual banks. Bank (0) size is 128kb, base address is 0x8000000
Warn : couldn't use loader, falling back to page memory writes
Info : Device: STM32L0xx (Cat.5)
Warn : STM32L flash bank base address config is incorrect. 0x8018000 but should rather be 0x8000000 or 0x8020000
Error: auto_probe failed
** Programming Failed **
shutdown command invoked
~~~


So I tried to fix things by rebuilding OpenOCD, and changed the size of
the first (and second) flash page in src/flash/nor/stm32lx.c:261 from
128 to 96 KiB:
~~~
{
.id = 0x447,
.revs = stm32_447_revs,
.num_revs = ARRAY_SIZE(stm32_447_revs),
.device_str = "STM32L0xx (Cat.5)",
.page_size = 128,
.pages_per_sector = 32,
.max_flash_size_kb = 192,
.first_bank_size_kb = 96, // 128,
.has_dual_banks = true,
.flash_base = 0x40022000,
.fsize_base = 0x1FF8007C,
},
~~~


That actually works for my hardware with the modified cfg script:
~~~
$ ~/git/openocd/src/openocd -f interface/stlink-v2.cfg -f ./stm32l0.cfg -c "program build/prj.elf reset exit verify" --search
~/git/openocd/tcl
Open On-Chip Debugger 0.10.0+dev-00093-g6b2acc02 (2017-03-18-23:04)
...
Info : Device: STM32L0xx (Cat.5)
Info : STM32L flash has dual banks. Bank (0) size is 96kb, base address is 0x8000000
Warn : couldn't use loader, falling back to page memory writes
Info : Device: STM32L0xx (Cat.5)
Info : STM32L flash has dual banks. Bank (1) size is 96kb, base address is 0x8018000
Info : ignoring flash probed value, using configured bank size: 96kbytes
...
** Verified OK **
** Resetting Target **
~~~


So I've asked on IRC and tried to submit a really simple patch for that:
http://openocd.zylin.com/#/c/4073/

But like Cezary pointed out: This **does not solve the problem of all STM32L0**
Category 5 (or 3) devices, since they all have a different memory layout...

See also:
http://openocd.zylin.com/#/c/3554/

STM32L0x1 Ref Manual: http://st.com/resource/en/reference_manual/DM00108282.pdf
STM32L0x2 Ref Manual: http://st.com/resource/en/reference_manual/DM00108281.pdf
STM32L0x3 Ref Manual: http://st.com/resource/en/reference_manual/DM00095744.pdf


I don't have access to other hardware to test things out nor enough knowledge
about OpenOCD to really fix the issue for all cases...


-----


Possible solutions that came to mind:

1) Don't use hardcoded size values. - Like Karl Palsson pointed out:
Using the probed flash size (fsize_base/flash_size_in_kb, 0x1FF8004C on STM32L0x2,
33.1.1 Flash size register) and the device ID (32.4.1 MCU device ID code,
stm32lx_read_id_code()), it should be possible to figure out the exact flash
memory layout (size, addresses, dual bank).

2) Hardcode the values for all possible combinations for all STM32L0 MCU
types/categories code the sizes.

3) Maybe the easiest: Make it possible to change first_bank_size_kb in a
config script? Or is this already possible somehow?


I'd like to help fixing this issue...


---

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[Aurelio Lucchesi]

Post by Cezary Gapiński
I hope so, that it should works for all listed devices if the reference manuals from ST are correct and I didn't have make any mistake :).

Yes it looks good, if i understand it correctly, you're solving the issue with different sizes/categories there:

~~~
/* Overwrite default dual-bank configuration */
switch (device_id & 0xfff) {
case 0x447: /* STM32L0xx (Cat.5) devices */
switch (flash_size_in_kb) {
case 192:
case 128:
stm32lx_info->part_info.first_bank_size_kb = flash_size_in_kb / 2;
break;
case 64:
stm32lx_info->part_info.has_dual_banks = false;
break;
}
break;
case 0x437: /* STM32L1xx (Cat.5/Cat.6) */
stm32lx_info->part_info.first_bank_size_kb = flash_size_in_kb / 2;
break;
}
~~~

Post by Cezary Gapiński
id = 0x447 STM32L0xx (Cat.5) <- dual bank, for flash size 192 or 128 KBytes, single bank for 64 KBytes
id = 0x436 STM32L1xx (Cat.4/Cat.3 - Medium+/High Density) <- only one size of bank, default values are correct
id = 0x437 STM32L1xx (Cat.5/Cat.6) <- always dual bank, but size of bank can be different

That sould do it! Just asking myself, why ST was not giving the different variants different IDs in the first place? (And what are these categories 1-5 exactly... I'm still learning about embedded dev, so I'm still a total newbie here...)

Post by Cezary Gapiński

Post by Cezary Gapiński
Or of course if you will have more clear idea with option bytes usage, I will be also perfectly happy to use your solution :).

It seems that the L0s don't have such a "dual bank bit" in their option bytes (FLASH_OPTR), like bigger STM32s do...

Post by Cezary Gapiński
http://openocd.zylin.com/#/c/3957/6/tcl/target/stm32l0_dual_bank.cfg

With the second bank defined like in the CFG above, it works fine here!

Post by Cezary Gapiński
Can you show the stm32l0.cfg file?

That one was just a copy of tcl/target/stm32l0.cfg to try things out.
The definition of the second bank was necessary to make it work here (stm32l0_dual_bank.cfg).

Post by Cezary Gapiński
BTW, you are using STM32L082 on custom board or this is some sort of evaluation board.
If it's eval board perhaps you can create a patch with yout board configuration?

It's a custom board, but I would have en eval board with the L0 too (B-L072Z-LRWAN1). I might test it there as well at some point, and add it as a board configuration, but probably it's a too exotic eval board to add to the offical repo...




---

** [tickets:#148] STM32L0x: flash size and dual bank support**

**Status:** new
**Milestone:** 0.9.0
**Created:** Sun Mar 19, 2017 01:47 AM UTC by Aurelio Lucchesi
**Last Updated:** Tue Mar 21, 2017 05:13 PM UTC
**Owner:** nobody


Flash programming large binaries to my STM32L082 board failed,
and I had to recompile OpenOCD in order to make it work.



Without modification, it looks like this:
~~~
$ openocd -f interface/stlink-v2.cfg -f target/stm32l0.cfg -c "program build/prj.elf reset exit verify"
...
Info : Device: STM32L0xx (Cat.5)
Info : STM32L flash has dual banks. Bank (0) size is 128kb, base address is 0x8000000
...
Error: checksum mismatch - attempting binary compare
diff 0 address 0x08020000. Was 0x3e instead of 0x69
diff 1 address 0x08020001. Was 0x79 instead of 0x21
diff 2 address 0x08020002. Was 0x79 instead of 0x3d
diff 3 address 0x08020003. Was 0x74 instead of 0x59
diff 4 address 0x08020004. Was 0x6f instead of 0x59
diff 5 address 0x08020005. Was 0x73 instead of 0x5f
...
~~~


Then I've realized that there are two flash program memory banks:

STM32L0xx category 5 MCUs come with 192 KiB of Flash program memory:
* Bank 1: starting at 0x0800 0000, size 96 KiB
* Bank 2: starting at 0x0801 8000, size 96 KiB

So I've added a second one to a copy of the stm32l0.cfg script:
~~~
# flash size will be probed
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME stm32lx 0x08000000 0 0 0 $_TARGETNAME

# add second flash bank
set _FLASHNAME $_CHIPNAME.flash1
flash bank $_FLASHNAME stm32lx 0x08018000 0x18000 0 0 $_TARGETNAME
~~~


But that revealed another problem:
~~~
$ openocd -f interface/stlink-v2.cfg -f ./stm32l0.cfg -c "program build/prj.elf reset exit verify"
...
Info : Device: STM32L0xx (Cat.5)
Info : STM32L flash has dual banks. Bank (0) size is 128kb, base address is 0x8000000
Warn : couldn't use loader, falling back to page memory writes
Info : Device: STM32L0xx (Cat.5)
Warn : STM32L flash bank base address config is incorrect. 0x8018000 but should rather be 0x8000000 or 0x8020000
Error: auto_probe failed
** Programming Failed **
shutdown command invoked
~~~


So I tried to fix things by rebuilding OpenOCD, and changed the size of
the first (and second) flash page in src/flash/nor/stm32lx.c:261 from
128 to 96 KiB:
~~~
{
.id = 0x447,
.revs = stm32_447_revs,
.num_revs = ARRAY_SIZE(stm32_447_revs),
.device_str = "STM32L0xx (Cat.5)",
.page_size = 128,
.pages_per_sector = 32,
.max_flash_size_kb = 192,
.first_bank_size_kb = 96, // 128,
.has_dual_banks = true,
.flash_base = 0x40022000,
.fsize_base = 0x1FF8007C,
},
~~~


That actually works for my hardware with the modified cfg script:
~~~
$ ~/git/openocd/src/openocd -f interface/stlink-v2.cfg -f ./stm32l0.cfg -c "program build/prj.elf reset exit verify" --search
~/git/openocd/tcl
Open On-Chip Debugger 0.10.0+dev-00093-g6b2acc02 (2017-03-18-23:04)
...
Info : Device: STM32L0xx (Cat.5)
Info : STM32L flash has dual banks. Bank (0) size is 96kb, base address is 0x8000000
Warn : couldn't use loader, falling back to page memory writes
Info : Device: STM32L0xx (Cat.5)
Info : STM32L flash has dual banks. Bank (1) size is 96kb, base address is 0x8018000
Info : ignoring flash probed value, using configured bank size: 96kbytes
...
** Verified OK **
** Resetting Target **
~~~


So I've asked on IRC and tried to submit a really simple patch for that:
http://openocd.zylin.com/#/c/4073/

But like Cezary pointed out: This **does not solve the problem of all STM32L0**
Category 5 (or 3) devices, since they all have a different memory layout...

See also:
http://openocd.zylin.com/#/c/3554/

STM32L0x1 Ref Manual: http://st.com/resource/en/reference_manual/DM00108282.pdf
STM32L0x2 Ref Manual: http://st.com/resource/en/reference_manual/DM00108281.pdf
STM32L0x3 Ref Manual: http://st.com/resource/en/reference_manual/DM00095744.pdf


I don't have access to other hardware to test things out nor enough knowledge
about OpenOCD to really fix the issue for all cases...


-----


Possible solutions that came to mind:

1) Don't use hardcoded size values. - Like Karl Palsson pointed out:
Using the probed flash size (fsize_base/flash_size_in_kb, 0x1FF8004C on STM32L0x2,
33.1.1 Flash size register) and the device ID (32.4.1 MCU device ID code,
stm32lx_read_id_code()), it should be possible to figure out the exact flash
memory layout (size, addresses, dual bank).

2) Hardcode the values for all possible combinations for all STM32L0 MCU
types/categories code the sizes.

3) Maybe the easiest: Make it possible to change first_bank_size_kb in a
config script? Or is this already possible somehow?


I'd like to help fixing this issue...


---

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[Uwe Bonnes]

Try connect under reset



---

** [tickets:#148] STM32L0x: flash size and dual bank support**

**Status:** new
**Milestone:** 0.9.0
**Created:** Sun Mar 19, 2017 01:47 AM UTC by Aurelio Lucchesi
**Last Updated:** Tue May 23, 2017 12:14 PM UTC
**Owner:** nobody


Flash programming large binaries to my STM32L082 board failed,
and I had to recompile OpenOCD in order to make it work.



Without modification, it looks like this:
~~~
$ openocd -f interface/stlink-v2.cfg -f target/stm32l0.cfg -c "program build/prj.elf reset exit verify"
...
Info : Device: STM32L0xx (Cat.5)
Info : STM32L flash has dual banks. Bank (0) size is 128kb, base address is 0x8000000
...
Error: checksum mismatch - attempting binary compare
diff 0 address 0x08020000. Was 0x3e instead of 0x69
diff 1 address 0x08020001. Was 0x79 instead of 0x21
diff 2 address 0x08020002. Was 0x79 instead of 0x3d
diff 3 address 0x08020003. Was 0x74 instead of 0x59
diff 4 address 0x08020004. Was 0x6f instead of 0x59
diff 5 address 0x08020005. Was 0x73 instead of 0x5f
...
~~~


Then I've realized that there are two flash program memory banks:

STM32L0xx category 5 MCUs come with 192 KiB of Flash program memory:
* Bank 1: starting at 0x0800 0000, size 96 KiB
* Bank 2: starting at 0x0801 8000, size 96 KiB

So I've added a second one to a copy of the stm32l0.cfg script:
~~~
# flash size will be probed
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME stm32lx 0x08000000 0 0 0 $_TARGETNAME

# add second flash bank
set _FLASHNAME $_CHIPNAME.flash1
flash bank $_FLASHNAME stm32lx 0x08018000 0x18000 0 0 $_TARGETNAME
~~~


But that revealed another problem:
~~~
$ openocd -f interface/stlink-v2.cfg -f ./stm32l0.cfg -c "program build/prj.elf reset exit verify"
...
Info : Device: STM32L0xx (Cat.5)
Info : STM32L flash has dual banks. Bank (0) size is 128kb, base address is 0x8000000
Warn : couldn't use loader, falling back to page memory writes
Info : Device: STM32L0xx (Cat.5)
Warn : STM32L flash bank base address config is incorrect. 0x8018000 but should rather be 0x8000000 or 0x8020000
Error: auto_probe failed
** Programming Failed **
shutdown command invoked
~~~


So I tried to fix things by rebuilding OpenOCD, and changed the size of
the first (and second) flash page in src/flash/nor/stm32lx.c:261 from
128 to 96 KiB:
~~~
{
.id = 0x447,
.revs = stm32_447_revs,
.num_revs = ARRAY_SIZE(stm32_447_revs),
.device_str = "STM32L0xx (Cat.5)",
.page_size = 128,
.pages_per_sector = 32,
.max_flash_size_kb = 192,
.first_bank_size_kb = 96, // 128,
.has_dual_banks = true,
.flash_base = 0x40022000,
.fsize_base = 0x1FF8007C,
},
~~~


That actually works for my hardware with the modified cfg script:
~~~
$ ~/git/openocd/src/openocd -f interface/stlink-v2.cfg -f ./stm32l0.cfg -c "program build/prj.elf reset exit verify" --search
~/git/openocd/tcl
Open On-Chip Debugger 0.10.0+dev-00093-g6b2acc02 (2017-03-18-23:04)
...
Info : Device: STM32L0xx (Cat.5)
Info : STM32L flash has dual banks. Bank (0) size is 96kb, base address is 0x8000000
Warn : couldn't use loader, falling back to page memory writes
Info : Device: STM32L0xx (Cat.5)
Info : STM32L flash has dual banks. Bank (1) size is 96kb, base address is 0x8018000
Info : ignoring flash probed value, using configured bank size: 96kbytes
...
** Verified OK **
** Resetting Target **
~~~


So I've asked on IRC and tried to submit a really simple patch for that:
http://openocd.zylin.com/#/c/4073/

But like Cezary pointed out: This **does not solve the problem of all STM32L0**
Category 5 (or 3) devices, since they all have a different memory layout...

See also:
http://openocd.zylin.com/#/c/3554/

STM32L0x1 Ref Manual: http://st.com/resource/en/reference_manual/DM00108282.pdf
STM32L0x2 Ref Manual: http://st.com/resource/en/reference_manual/DM00108281.pdf
STM32L0x3 Ref Manual: http://st.com/resource/en/reference_manual/DM00095744.pdf


I don't have access to other hardware to test things out nor enough knowledge
about OpenOCD to really fix the issue for all cases...


-----


Possible solutions that came to mind:

1) Don't use hardcoded size values. - Like Karl Palsson pointed out:
Using the probed flash size (fsize_base/flash_size_in_kb, 0x1FF8004C on STM32L0x2,
33.1.1 Flash size register) and the device ID (32.4.1 MCU device ID code,
stm32lx_read_id_code()), it should be possible to figure out the exact flash
memory layout (size, addresses, dual bank).

2) Hardcode the values for all possible combinations for all STM32L0 MCU
types/categories code the sizes.

3) Maybe the easiest: Make it possible to change first_bank_size_kb in a
config script? Or is this already possible somehow?


I'd like to help fixing this issue...


---

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[Rui Carvalho]

Thanks Uwe! Now it works if you keep pressing the reset button!

But after running "telnet localhost 4444", what commands work for lock/unlock and read/write flash?

I tried:
~~~

stm32lx unlock 0

Cannot identify target as a STM32L family.
auto_probe failed

stm32f2 unlock 0

invalid command name "stm32f2"

stm32f2x unlock 0

invalid command name "stm32f2x"

stm32f2x options_read 0

invalid command name "stm32f2x"

stm32 options_read 0

invalid command name "stm32"

stm32l options_read 0

invalid command name "stm32l"

stm32lx options_read 0

invalid subcommand "options_read 0"
in procedure 'stm32lx'

dump_image dump_flash.bin 0x08000000 0x80000

dumped 524288 bytes in 27.198000s (18.825 KiB/s)
~~~

but had no success and the dump_flash.bin file generated is all 0000... (zeros) when it should be the default program running in the devkit.

Any help?


---

** [tickets:#148] STM32L0x: flash size and dual bank support**

**Status:** new
**Milestone:** 0.9.0
**Created:** Sun Mar 19, 2017 01:47 AM UTC by Aurelio Lucchesi
**Last Updated:** Tue May 23, 2017 12:34 PM UTC
**Owner:** nobody


Flash programming large binaries to my STM32L082 board failed,
and I had to recompile OpenOCD in order to make it work.



Without modification, it looks like this:
~~~
$ openocd -f interface/stlink-v2.cfg -f target/stm32l0.cfg -c "program build/prj.elf reset exit verify"
...
Info : Device: STM32L0xx (Cat.5)
Info : STM32L flash has dual banks. Bank (0) size is 128kb, base address is 0x8000000
...
Error: checksum mismatch - attempting binary compare
diff 0 address 0x08020000. Was 0x3e instead of 0x69
diff 1 address 0x08020001. Was 0x79 instead of 0x21
diff 2 address 0x08020002. Was 0x79 instead of 0x3d
diff 3 address 0x08020003. Was 0x74 instead of 0x59
diff 4 address 0x08020004. Was 0x6f instead of 0x59
diff 5 address 0x08020005. Was 0x73 instead of 0x5f
...
~~~


Then I've realized that there are two flash program memory banks:

STM32L0xx category 5 MCUs come with 192 KiB of Flash program memory:
* Bank 1: starting at 0x0800 0000, size 96 KiB
* Bank 2: starting at 0x0801 8000, size 96 KiB

So I've added a second one to a copy of the stm32l0.cfg script:
~~~
# flash size will be probed
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME stm32lx 0x08000000 0 0 0 $_TARGETNAME

# add second flash bank
set _FLASHNAME $_CHIPNAME.flash1
flash bank $_FLASHNAME stm32lx 0x08018000 0x18000 0 0 $_TARGETNAME
~~~


But that revealed another problem:
~~~
$ openocd -f interface/stlink-v2.cfg -f ./stm32l0.cfg -c "program build/prj.elf reset exit verify"
...
Info : Device: STM32L0xx (Cat.5)
Info : STM32L flash has dual banks. Bank (0) size is 128kb, base address is 0x8000000
Warn : couldn't use loader, falling back to page memory writes
Info : Device: STM32L0xx (Cat.5)
Warn : STM32L flash bank base address config is incorrect. 0x8018000 but should rather be 0x8000000 or 0x8020000
Error: auto_probe failed
** Programming Failed **
shutdown command invoked
~~~


So I tried to fix things by rebuilding OpenOCD, and changed the size of
the first (and second) flash page in src/flash/nor/stm32lx.c:261 from
128 to 96 KiB:
~~~
{
.id = 0x447,
.revs = stm32_447_revs,
.num_revs = ARRAY_SIZE(stm32_447_revs),
.device_str = "STM32L0xx (Cat.5)",
.page_size = 128,
.pages_per_sector = 32,
.max_flash_size_kb = 192,
.first_bank_size_kb = 96, // 128,
.has_dual_banks = true,
.flash_base = 0x40022000,
.fsize_base = 0x1FF8007C,
},
~~~


That actually works for my hardware with the modified cfg script:
~~~
$ ~/git/openocd/src/openocd -f interface/stlink-v2.cfg -f ./stm32l0.cfg -c "program build/prj.elf reset exit verify" --search
~/git/openocd/tcl
Open On-Chip Debugger 0.10.0+dev-00093-g6b2acc02 (2017-03-18-23:04)
...
Info : Device: STM32L0xx (Cat.5)
Info : STM32L flash has dual banks. Bank (0) size is 96kb, base address is 0x8000000
Warn : couldn't use loader, falling back to page memory writes
Info : Device: STM32L0xx (Cat.5)
Info : STM32L flash has dual banks. Bank (1) size is 96kb, base address is 0x8018000
Info : ignoring flash probed value, using configured bank size: 96kbytes
...
** Verified OK **
** Resetting Target **
~~~


So I've asked on IRC and tried to submit a really simple patch for that:
http://openocd.zylin.com/#/c/4073/

But like Cezary pointed out: This **does not solve the problem of all STM32L0**
Category 5 (or 3) devices, since they all have a different memory layout...

See also:
http://openocd.zylin.com/#/c/3554/

STM32L0x1 Ref Manual: http://st.com/resource/en/reference_manual/DM00108282.pdf
STM32L0x2 Ref Manual: http://st.com/resource/en/reference_manual/DM00108281.pdf
STM32L0x3 Ref Manual: http://st.com/resource/en/reference_manual/DM00095744.pdf


I don't have access to other hardware to test things out nor enough knowledge
about OpenOCD to really fix the issue for all cases...


-----


Possible solutions that came to mind:

1) Don't use hardcoded size values. - Like Karl Palsson pointed out:
Using the probed flash size (fsize_base/flash_size_in_kb, 0x1FF8004C on STM32L0x2,
33.1.1 Flash size register) and the device ID (32.4.1 MCU device ID code,
stm32lx_read_id_code()), it should be possible to figure out the exact flash
memory layout (size, addresses, dual bank).

2) Hardcode the values for all possible combinations for all STM32L0 MCU
types/categories code the sizes.

3) Maybe the easiest: Make it possible to change first_bank_size_kb in a
config script? Or is this already possible somehow?


I'd like to help fixing this issue...


---

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[Rui Carvalho]

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