[Openocd-development] feroceon-based target bring-up issue

[Albert ARIBAUD]

Hi,

I am trying to bring-up an ED Mini V2, a feroceon-based board with no
tRST/sRST signals available, only TCLK/TMS/TDI/TDO, and an Olimex
ARM-USB-OCD.

This ED-Mini has a working U-boot flashed already (I am aiming at
replacing this U-boot with a newer version).

To begin with, I've made a basic config file, containing only the two

source [find tcl/interface/olimex-arm-usb-ocd.cfg]
source [find tcl/target/feroceon.cfg]
reset_config none

Using the latest git version of openocd, if I start it with the config

$ src/openocd -f o.cfg
Open On-Chip Debugger 0.4.0-dev-00171-gfd2c9fd (2009-11-24-08:48)
For bug reports, read
http://openocd.berlios.de/doc/doxygen/bugs.html
trst_and_srst separate srst_gates_jtag trst_push_pull srst_open_drain
jtag_nsrst_delay: 200
jtag_ntrst_delay: 200
Info : clock speed 6000 kHz
Info : JTAG tap: feroceon.cpu tap/device found: 0x49602093 (mfg: 0x049, part: 0x9602, ver: 0x4)
Warn : JTAG tap: feroceon.cpu UNEXPECTED: 0x49602093 (mfg: 0x049, part: 0x9602, ver: 0x4)
Error: JTAG tap: feroceon.cpu expected 1 of 1: 0x20a023d3 (mfg: 0x1e9, part: 0x0a02, ver: 0x2)
Error: Trying to use configured scan chain anyway...
Error: feroceon.cpu: IR capture error; saw 0x09 not 0x01
Info : JTAG tap: feroceon.cpu tap/device found: 0x49602093 (mfg: 0x049, part: 0x9602, ver: 0x4)
Warn : JTAG tap: feroceon.cpu UNEXPECTED: 0x49602093 (mfg: 0x049, part: 0x9602, ver: 0x4)
Error: JTAG tap: feroceon.cpu expected 1 of 1: 0x20a023d3 (mfg: 0x1e9, part: 0x0a02, ver: 0x2)
Error: Trying to use configured scan chain anyway...
Error: feroceon.cpu: IR capture error; saw 0x09 not 0x01

(all jtag clock speeds give the same exact output)

The UNEXPECTED line worries me, but since errata for the 88F5182-A2 SoC
says IDCODE should not be relied upon, I used the mechanism already in

source [find tcl/interface/olimex-arm-usb-ocd.cfg]
set CPUTAPID 0x49602093
source [find tcl/target/feroceon.cfg]
reset_config none
$ src/openocd -f o.cfg
Open On-Chip Debugger 0.4.0-dev-00171-gfd2c9fd (2009-11-24-08:48)
For bug reports, read
http://openocd.berlios.de/doc/doxygen/bugs.html
trst_and_srst separate srst_gates_jtag trst_push_pull srst_open_drain
jtag_nsrst_delay: 200
jtag_ntrst_delay: 200
none separate
Info : clock speed 6000 kHz
Info : JTAG tap: feroceon.cpu tap/device found: 0x49602093 (mfg: 0x049, part: 0x9602, ver: 0x4)
Error: feroceon.cpu: IR capture error; saw 0x09 not 0x01
Info : JTAG tap: feroceon.cpu tap/device found: 0x49602093 (mfg: 0x049, part: 0x9602, ver: 0x4)
Error: feroceon.cpu: IR capture error; saw 0x09 not 0x01

The target still resets at openocd launch. I first thought this was a
default behavior for OpenOCD, but I still get the IR capture errors and

$ telnet localhost 4444
Trying 127.0.0.1...
Connected to localhost.localdomain (127.0.0.1).
Escape character is '^]'.
Open On-Chip Debugger

targets

TargetName Type Endian TapName State
-- ------------------ ---------- ------ ------------------ ------------
0* feroceon.cpu feroceon little feroceon.cpu unknown

feroceon.cpu arp_examine

Embedded ICE version 0
unexpected Feroceon EICE version signature

targets

TargetName Type Endian TapName State
-- ------------------ ---------- ------ ------------------ ------------
0* feroceon.cpu feroceon little feroceon.cpu running

halt

Halt timed out, wake up GDB.
timed out while waiting for target halted

targets

TargetName Type Endian TapName State
-- ------------------ ---------- ------ ------------------ ------------
0* feroceon.cpu feroceon little feroceon.cpu running

At this point I am unsure if the issue is at the JTAG level itself or in
the E-ICE scan chain level, or in the board itself.

I've tried using irscan and drscan for, e.g., re-reading the IDCODE

irscan feroceon.cpu 0xe
drscan feroceon.cpu 32 0

00000000

drscan feroceon.cpu 32 0

00000000
...

But I believe jtag is not correctly reset when I try this, because jtag
arp_init and jtag arp_init-reset both scan the chain and thus may not
leave the TAP in reset mode -- by the way, a scan_chain does not reset
the board (a jtag arp_init or arp_init-reset does).

Can someone give me pointers to where I should look (in OpenOCD) in
order to progressively debug the situation?

Amicalement,

[David Brownell]

Error: feroceon.cpu: IR capture error; saw 0x09 not 0x01

jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
^^^^^^^^^^^
Does "0x03" behave?

[Albert ARIBAUD]

Post by David Brownell

Error: feroceon.cpu: IR capture error; saw 0x09 not 0x01

jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
^^^^^^^^^^^
Does "0x03" behave?

I did investigate by fixing 0x3 directly in feroceon.cfg, and it does

Post by David Brownell
Error: IR capture error at bit 4, saw 0x09 not 0x...3

(and it does not change anything else -- this is consistent with the
OpenOCD docs, which state that IR capture is for information only and
has no functional impact.)

Actually, a combination that works (i.e., shows no IR capture error) is
obtained by using -irlen 32 -ircapture 0x1 -irmask 0x3, but an IR length
of 32 is inconsistent with the ARM/feroceon literature available (in
which IR length is 4 bits). Besides, other OpenOCD users have working
configs with feroceon.cfg as it is (on another board type and/or another
JTAG probe type).

With that abnormal -irlen 32 -ircapture 0x1 -irmask 0x3, the behavior is

Post by David Brownell
$ src/openocd -f o.cfg
Open On-Chip Debugger 0.4.0-dev-00171-gfd2c9fd (2009-11-24-08:48)
For bug reports, read
http://openocd.berlios.de/doc/doxygen/bugs.html
trst_and_srst separate srst_gates_jtag trst_push_pull srst_open_drain
jtag_nsrst_delay: 200
jtag_ntrst_delay: 200
none separate
Info : clock speed 6000 kHz
Info : JTAG tap: feroceon.cpu tap/device found: 0x49602093 (mfg: 0x049, part: 0x9602, ver: 0x4)
Info : Embedded ICE version 12
Error: unexpected Feroceon EICE version signature

And the target seems to halt (no reaction on the U-boot serial console)
but still appears running in the telnet interface, and still cannot be
halted

Note that if I then do a ^C and launch openOCD again, the "Unexpected
Feroceon EICE version signature" message does not appear again.

Amicalement,

[David Brownell]

Post by Albert ARIBAUD
I did investigate by fixing 0x3 directly in feroceon.cfg, and it does

Post by David Brownell
Error: IR capture error at bit 4, saw 0x09 not 0x...3

Are you sure you didn't make the "ircapture" be 0x3,
instead of the "irmask"? Because masking the two LSBs (0x3)
of 0x09 gives 0x01, the specified "ircapture" value.

[Albert ARIBAUD]

Post by David Brownell

Post by Albert ARIBAUD
I did investigate by fixing 0x3 directly in feroceon.cfg, and it does

Post by David Brownell
Error: IR capture error at bit 4, saw 0x09 not 0x...3

Are you sure you didn't make the "ircapture" be 0x3,
instead of the "irmask"? Because masking the two LSBs (0x3)
of 0x09 gives 0x01, the specified "ircapture" value.
jtag newtap $_CHIPNAME cpu -irlen 32 -ircapture 0x1 -irmask 0x3 -expected-id $_CPUTAPID

This is what gave the results I gave in my previous post.

Amicalement,

[Albert ARIBAUD]

Post by Albert ARIBAUD

Post by David Brownell

Post by Albert ARIBAUD
I did investigate by fixing 0x3 directly in feroceon.cfg, and it does

Post by David Brownell
Error: IR capture error at bit 4, saw 0x09 not 0x...3

Are you sure you didn't make the "ircapture" be 0x3,
instead of the "irmask"? Because masking the two LSBs (0x3)
of 0x09 gives 0x01, the specified "ircapture" value.
jtag newtap $_CHIPNAME cpu -irlen 32 -ircapture 0x1 -irmask 0x3 -expected-id $_CPUTAPID

This is what gave the results I gave in my previous post.

Added info: I tried putting the JTAG in BYPASS and then shift data

Post by Albert ARIBAUD
irscan feroceon.cpu 0xf
drscan feroceon.cpu 32 0xffaa0055
C0E28618

Post by David Brownell
drscan feroceon.cpu 32 0

C0E28618

Post by David Brownell
drscan feroceon.cpu 32 0xffffffff

C0E28618

So, obviously, -irlen 32 is not correct (that was to be expected).

Post by Albert ARIBAUD

Post by David Brownell
irscan feroceon.cpu 0xf
drscan feroceon.cpu 32 0xffaa0055

FF5400AA

Post by David Brownell
drscan feroceon.cpu 32 0

00000000

Post by David Brownell
drscan feroceon.cpu 32 0xffffffff

FFFFFFFE

That's way better, and seems to work as described by e.g. ARM9EJ-S TRM
annex B.4: TDO is TDI with a 1-bit left shift, and MSB forced at 0.

So now I'm completely sure the right irlen setting is 4.

Still, I cannot talk to the target, and even trying to get IDCODE does
not work -- weirder yet:

- doing an "irscan feroceon.cpu 0xe" right after my BYPASS test causes a
target reboot;

- doing it after a "jtag arp_init" does not reboot, but then a drscan
0x32 0 returns 0, which is not the IDCODE seen by OpenOCD.

Amicalement,