[OpenOCD-devel] multiple cores on a single TAP

[Tim Newsome]

RISC-V supports accessing more than one core through a single JTAG TAP. Is
there an existing example in OpenOCD of a target that does the same thing?
Failing that, has this been considered and is there a suggested way to go
about implementing it?

Tim

[Andreas Färber]

Post by Tim Newsome
RISC-V supports accessing more than one core through a single JTAG TAP.
Is there an existing example in OpenOCD of a target that does the same
thing?

http://openocd.org/doc/html/Config-File-Guidelines.html -> 6.3.4

HTH,
Andreas

[Tim Newsome]

Thanks. That looks promising. I'll play with it for real once I have a
target that has more than one core. I'm happy that this infrastructure
exists.

Tim

Post by Andreas Färber

Post by Tim Newsome
RISC-V supports accessing more than one core through a single JTAG TAP.
Is there an existing example in OpenOCD of a target that does the same
thing?

http://openocd.org/doc/html/Config-File-Guidelines.html -> 6.3.4
HTH,
Andreas
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[Tim Newsome]

I'm finally looking at this again. :-)

SMP isn't quite the behavior I would like. Specifically, it would be nice
to halt/resume different cores independently, and hardware breakpoints are
also unique per core.

To recap the problem:
On RISC-V multiple core use the same JTAG TAP. These cores will all be
RISC-V, but otherwise can vary arbitrarily (eg. one can be 32-bit, another
can be 64-bit, and they may even have different views of RAM). Switching
between cores happens by performing a JTAG scan. (More advanced features
allow to select multiple cores at once to facilitate simultaneous
run/halt/step, but I don't expect OpenOCD to support that.)
How can I make this work with OpenOCD? We're playing with a hack by
exposing multiple cores as OS threads, but that's not quite right.

Tim

Post by Tim Newsome
Thanks. That looks promising. I'll play with it for real once I have a
target that has more than one core. I'm happy that this infrastructure
exists.
Tim

Post by Andreas Färber

Post by Tim Newsome
RISC-V supports accessing more than one core through a single JTAG TAP.
Is there an existing example in OpenOCD of a target that does the same
thing?

http://openocd.org/doc/html/Config-File-Guidelines.html -> 6.3.4
HTH,
Andreas
--
SUSE Linux GmbH, Maxfeldstr. 5, 90409 NÃŒrnberg, Germany
GF: Felix Imendörffer, Jane Smithard, Graham Norton
HRB 21284 (AG NÃŒrnberg)
------------------------------------------------------------
------------------
Mobile security can be enabling, not merely restricting. Employees who
bring their own devices (BYOD) to work are irked by the imposition of MDM
restrictions. Mobile Device Manager Plus allows you to control only the
apps on BYO-devices by containerizing them, leaving personal data
untouched!
https://ad.doubleclick.net/ddm/clk/304595813;131938128;j
_______________________________________________
OpenOCD-devel mailing list
https://lists.sourceforge.net/lists/listinfo/openocd-devel

[Andreas Fritiofson]

Hi!

Post by Tim Newsome
I'm finally looking at this again. :-)
SMP isn't quite the behavior I would like. Specifically, it would be nice
to halt/resume different cores independently, and hardware breakpoints are
also unique per core.
On RISC-V multiple core use the same JTAG TAP. These cores will all be
RISC-V, but otherwise can vary arbitrarily (eg. one can be 32-bit, another
can be 64-bit, and they may even have different views of RAM).

That sounds more like a regular multi-target setup than one multi-core
target. This would normally be handled with one target defined per core,
one gdb server per core etc. They are all completely independent of each
other, separate breakpoints and everything.

Is there any reason you'd want to treat it as a single SMP target?

Post by Tim Newsome
Switching between cores happens by performing a JTAG scan.

Basically the same principle as ARM DAP I guess, so you'd need a layer
between the targets and the TAP. Just don't copy the DAP code straight
away, it suffers from some architectural flaws that are hard to fix at this
point.

(More advanced features allow to select multiple cores at once to

Post by Tim Newsome
facilitate simultaneous run/halt/step, but I don't expect OpenOCD to
support that.)
How can I make this work with OpenOCD? We're playing with a hack by
exposing multiple cores as OS threads, but that's not quite right.

Neat, but imagine the mess if you'd want to run a real OS awareness on top
of that... :)

/Andreas